Recently, owing to the tendency of electric and electronic components to be small and thin, IC and LSI packages have become varied. Especially, while the size of a chip has become larger, the package has become thinner and varied with high pin numbers.
The mounting technology has also varied according to surface mounting technology. Recently, Thin Small Out-line J-Bend Packages(TSOJ) having a thickness of about 1 mm are being produced. TSOJ, which is a medium stage type between a Small Out-line J-Bend Package(SOJ)/Quad Flat Package(QFP) and a Tape Automated Bonding(TAB), will be used as the main type of package in the memory element field in the near future.
The resin composition for sealing such semiconductor elements requires strict low stress, high heat and moisture resistant properties over the prior art compositions.
The method for decreasing inner stress by adding plasticizers such as a modified silicone oil or CTBN[Japanese Laid-open Patent Publication Nos. (Sho) 63-230725, 62-7723, 62-132961 and 62-260817] and the method for lowering the thermal expansion coefficient by increasing the amounts of fillers [Japanese Laid-open Patent Publication No. (Sho) 62-106920] are known as low stress techniques. However, such methods have serious problems such as low heat resistance, moldability and abrasion of equipment.
The method for improving heat resistance by using polyfunctional epoxy resins [Japanese Laid-open Patent Publication Nos. (Sho) 62-477, 62-7719 and 62-7723] and the method for increasing heat resistance by using a bismaleimide [Japanese Laid-open Patent Publication Nos. (Sho) 54-142298 and 58-215452] are well known. However, these methods have problems in that due to an increase in the glass transition temperature of the resin composition the moisture resistant property decreases.